The present invention relates to a semiconductor memory device (hereinafter referred to as memory), and particularly to a technique that can be effectively adapted to, for example, a dynamic random access memory (hereinafter referred to as dynamic RAM) having a large storage capacity.
A dynamic RAM has memory arrays consisting of a plurality of memory cells, and address decoder circuits for selecting memory cells that are designated by address signals out of the memory arrays.
In the dynamic RAM, each memory cell consists of an insulated gate field effect transistor (hereinafter referred to as MOSFET) and a capacitor. Since the memory cell is made up of a relatively small number of elements, it is allowed to form many memory cells on a semiconductor chip relatively easily, and to realize a memory having a large storage capacity.
However, increase in the number of memory cells formed on the semiconductor chip results in the increase in the number of elements which constitute an address decoder circuit to select desired memory cells out of the memory array. In other words, an increased area is occupied by the address decoder circuit. The increase in the area occupied by the address decoder circuit imposes a limitation when a memory having a large storage capacity is to be formed on a relatively small semiconductor chip.
FIG. 8 is a diagram of an address decoder circuit that was developed earlier by the inventors of the present invention. The address decoder circuit of FIG. 8 is used for the X system in a dynamic RAM having a storage capacity of, for example, about 256 K (262144) bits.
The dynamic RAM of 256 kilobits is constituted by four memory arrays each having a storage capacity of 64 K (65536) bits. Each of these memory arrays has 65536 memory cells arranged in the form of a matrix, data lines provided for each of the memory cell rows, and word lines provided for each of the memory cell columns. In this case, each of the memory arrays has, for example, 256 data lines and 256 word lines W.sub.0 to W.sub.255.
In the address decoder circuit of FIG. 8, word lines designated by address signals are selected out of 256 word lines, and select signals are supplied to the selected word lines only. Therefore, select signals are supplied from the address decoder circuit to the memory cells that are to be selected.
Further, the address decoder circuit is commonly used for the two memory arrays. Therefore, the above-mentioned dynamic RAM of 256 kilobits is provided with two address decoder circuits shown in FIG. 8. The address decoder circuit has a first address decoder circuit DEC.sub.1 and a second address decoder circuit DEC.sub.2.
The first address decoder circuit DEC.sub.1 consists of four unit address decoder circuits DEC.sub.10 to DEC.sub.13, receives complementary address signals ax0, ax1 and decodes them. Among the MOSFET's Q.sub.100 to Q.sub.103, therefore, a MOSFET designated by the complementary address signals ax0, ax1 is selected. Therefore, a select timing signal is selectively formed from the four select timing signals .phi..sub.x00 to .phi..sub.x11. Namely, 64 word lines are selected out of 256 word lines. A word line is selected by the second address decoder circuit DEC.sub.2 out of the above-selected 64 word lines. That is, the second address decoder circuit DEC.sub.2 decodes complementary address signals ax2 to ax7, receives through its one terminal the select timing signal formed respective to the decoded signal, and produces an output from the other terminal thereof to turn on a MOSFET that is coupled to a word line which is to be selected. Therefore, the select timing signal is transmitted only to a word line that is to be selected. The second address decoder circuit DEC.sub.2 consists of 64 unit address decoder circuits DEC.sub.200 to DEC.sub.263 to select a word line out of 64 word lines. Since the unit address decoder circuits are required in such a large number, the electric power is consumed in relatively large amounts.
The above-mentioned complementary address signal an consists of a pair of internal address signals, i.e., consists of an internal address signal an which is substantially in phase with an external address signal An supplied from an external unit, and an internal address signal an which is substantially inverted in phase relative to the external address signal An. Therefore, the complementary address signal ax0 consists of an internal complementary address signal ax0 and an internal address signal ax0 which is inverted in phase relative thereto. In the following description, therefore, the address signals are expressed in the above-mentioned manner.
The internal complementary address signals ax0 to ax7 are formed by an address buffer circuit which is not diagrammed. The internal complementary address signals ax2 to ax7 are supplied to relatively many number of unit address decoder circuits as mentioned above. Therefore, the load of address buffer circuit increases. Consequently, the address buffer circuit requires a relatively extended period of time to form internal complementary address signals, and operation speed of the dynamic RAM decreases.
MOSFET's Q.sub.100 to Q.sub.119 shown in FIG. 8 are all of the n-channel enhancement-type. In the following description, MOSFET's will be all of the n-channel enhancement-type unless stated otherwise.